Applying the Scheduler Test Case Technique to Verify Scheduler Implementations in Multi-Processor Time-Triggered Embedded Systems

We have recently introduced a technique called “scheduler test case” (STC) as a practical means for bridging the gap between scheduling algorithms and scheduler implementations in time-triggered embedded systems. The technique was originally applied to single-processor embedded designs employing “time-triggered co-operative” (TTC) architectures aimed at highly predictable real-time systems. It only makes sense to generalize the STC concept if its applicability in more complicated systems is proven. The study detailed in the present paper explores one way in which the STC technique can be adapted to assess the behaviour of timetriggered scheduling algorithms in multi-processor embedded systems. The particular systems considered are those which employ TTC schedulers (for task scheduling in each microcontroller node) and a “shared-clock” (SC) scheduling protocol (for message scheduling) when system nodes are connected via Controller Area Network (CAN) protocol. In more detail, the paper proposes a set of generic “scheduler test cases” (STCs) for exploring the impact of various time-triggered S-C scheduler implementations when run on specific hardware platform. The results of the paper demonstrate that the STC concept developed previously is also useful (and can be adopted) when more sophisticated real-time scheduling algorithms are implemented in low-cost embedded systems.